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NAOSITE : Nagasaki University's Academic Output SITE > Faculty of Engineering > Bulletin > Reports of the Faculty of Engineering, Nagasaki University > Volume 26, No. 47 >


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Title: ハードウエア記述言語による電圧形インバータ用PWM発生回の開発
Other Titles: Development of PWM Generator for Voltage-Type Inverter using Hardware Description Language
Authors: 泉, 勝弘 / 古川, 雄一朗 / 辻, 峰男 / 小山, 純 / 山田, 英二
Authors (alternative): Izumi, Katsuhiro / Furukawa, Yuichirou / Tsuji, Mineo / Oyama, Jun / Yamada, Eiji
Issue Date: Jul-1996
Citation: 長崎大学工学部研究報告 Vol.26(47) p. 191-195, 1996
Abstract: This paper presents a compact and high confident PWM generator with field programmable gate array (FPGA) to control high speed switching devices. FPGAs which have a large scale and big capacity are designed using hardware description language (HDL) in the field. Method of PWM pattern generation is asynchronous-type PWM, because hardware and software of it becomes simple. This FPGA contains many data latches, four counters and many logic. PWM generator with FPGA inputs the duty data and dead time one from a host processor and outputs the gate signal to the power device. We generate PWM patterns with a double edge modulation, and provide a variable dead time for prevent of upper and lower arm short-circuit. Experimental results are shown to verify functions of PWM generator with FPGA.
URI: http://hdl.handle.net/10069/14979
ISSN: 02860902
Type: Departmental Bulletin Paper
Appears in Collections:Volume 26, No. 47

Citable URI : http://hdl.handle.net/10069/14979

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