DSpace university logo mark
Japanese | English 

NAOSITE : Nagasaki University's Academic Output SITE > 060 工学部・工学研究科 > 060 会議発表資料 >

Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation

ファイル 記述 サイズフォーマット
FPL2011_478.pdf347.83 kBAdobe PDF本文ファイル

タイトル: Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation
著者: Dohi, Keisuke / Yorita, Yuji / Shibata, Yuichiro / Oguri, Kiyoshi
発行日: 2011年 9月
出版者: IEEE
引用: FPL 2011, pp.478-481
抄録: This paper shows stream-oriented FPGA implementation of the machine-learned Features from Accelerated Segment Test (FAST) corner detection, which is used in the parallel tracking and mapping (PTAM) for augmented reality (AR). One of the difficulties of compact hardware implementation of the FAST corner detection is a matching process with a large number of corner patterns. We propose corner pattern compression methods focusing on discriminant division and pattern symmetry for rotation and inversion. This pattern compression enables implementation of the corner pattern matching with a combinational circuit. Our prototype implementation achieves real-time execution performance with 7∼9% of available slices of a Virtex-5 FPGA.
記述: 2011 International Conference on Field Programmable Logic and Applications (FPL) : Chania, Greece, 2011.09.5-2011.09.7
URI: http://hdl.handle.net/10069/26676
ISBN: 978-1-4577-1484-9
DOI: 10.1109/FPL.2011.94
権利: © 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
資料タイプ: Conference Paper
原稿種類: author
出現コレクション:060 会議発表資料

引用URI : http://hdl.handle.net/10069/26676



Valid XHTML 1.0! Copyright © 2006-2015 長崎大学附属図書館 - お問い合わせ Powerd by DSpace