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Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation


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Title: Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation
Authors: Dohi, Keisuke / Yorita, Yuji / Shibata, Yuichiro / Oguri, Kiyoshi
Issue Date: Sep-2011
Publisher: IEEE
Citation: FPL 2011, pp.478-481
Abstract: This paper shows stream-oriented FPGA implementation of the machine-learned Features from Accelerated Segment Test (FAST) corner detection, which is used in the parallel tracking and mapping (PTAM) for augmented reality (AR). One of the difficulties of compact hardware implementation of the FAST corner detection is a matching process with a large number of corner patterns. We propose corner pattern compression methods focusing on discriminant division and pattern symmetry for rotation and inversion. This pattern compression enables implementation of the corner pattern matching with a combinational circuit. Our prototype implementation achieves real-time execution performance with 7∼9% of available slices of a Virtex-5 FPGA.
Description: 2011 International Conference on Field Programmable Logic and Applications (FPL) : Chania, Greece, 2011.09.5-2011.09.7
URI: http://hdl.handle.net/10069/26676
ISBN: 978-1-4577-1484-9
DOI: 10.1109/FPL.2011.94
Rights: © 2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Type: Conference Paper
Text Version: author
Appears in Collections:Conference Paper

Citable URI : http://hdl.handle.net/10069/26676

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