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Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm


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タイトル: Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm
著者: Negi, Kazuhiro / Dohi, Keisuke / Shibata, Yuichiro / Oguri, Kiyoshi
発行日: 2011年12月
出版者: IEEE
引用: 2011 International Conference on Field-Programmable Technology, FPT 2011, Article number6132679; 2011
抄録: In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves 62.5 fps of the detection throughput, showing 96.6% and 20.7% of the detection rate and the false positive rate, respectively. Moreover, if a highspeed camera device is available, the maximum throughput of 112 fps is expected to be accomplished, which is 7.5 times faster than software implementation.
キーワード: Detection rates / Empirical evaluations / External memory / False positive rates / FPGA implementations / Human detection / Image-based / Maximum through-put / Off-line training / Software implementation
URI: http://hdl.handle.net/10069/29887
DOI: 10.1109/FPT.2011.6132679
権利: © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
資料タイプ: Conference Paper
原稿種類: author
出現コレクション:060 会議発表資料

引用URI : http://hdl.handle.net/10069/29887

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